nsu1_perf_filter_0_1 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu1_perf_filter_0_1 (DDRMC_NOC) Register Description

Register Namensu1_perf_filter_0_1
Offset Address0x0000000524
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance monitor filter set 0 NSU1

nsu1_perf_filter_0_1 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src_id11:0rwNormal read/write0x0AxID