HBMMC_NA1 Module

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID

AM019

Release Date

2023-11-17

Revision

1.1

HBMMC_NA1 Module Description

Module Name	HBMMC_NA1 Module
Base Addresses	This module description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Description	High Bandwidth Memory Controller NoC Agent 1

HBMMC_NA1 Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
REG_PCSR_LOCK	0x000000000C	32	rwNormal read/write	0x00000001	NPI Lock Register
REG_ISR	0x0000000010	32	wtcReadable, write a 1 to clear	0x00000000	Interrupt Status Register. This is a sticky register set by HW on corresponding Error and will get cleared once PMV Writes a 1.
REG_ITR	0x0000000014	32	woWrite-only	0x00000000	Interrupt Status Register. Setting this bit to 1 will provide SW to trigger and Interrupt.
REG_IDR0	0x0000000018	32	woWrite-only	0x00000000	Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
REG_IDR1	0x000000001C	32	woWrite-only	0x00000000	Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
REG_IER0	0x0000000020	32	woWrite-only	0x00000000	Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
REG_IER1	0x0000000024	32	woWrite-only	0x00000000	Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
REG_IMR0	0x0000000028	32	roRead-only	0x0DFFFFFF	Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.
REG_IMR1	0x000000002C	32	roRead-only	0x0DFFFFFF	Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.
REG_IOR	0x0000000030	32	rwNormal read/write	0x00000005	Interrupt Offset Register. 5-bit offset for the interrupt mapping is provided by this register.
HBMMC_NA1_JEDEC_DEVICE_CODE	0x0000000128	32	rwNormal read/write	0x0000000A	HBM Device JEDEC Density Code
HBMMC_NA1_SCRUB_START_ADDRESS	0x0000000130	32	rwNormal read/write	0x00000000	Start address for scrub region and initialization
HBMMC_NA1_SCRUB_END_ADDRESS	0x0000000134	32	rwNormal read/write	0x0000000E	End address for scrub region and initialization
HBMMC_NA1_SCRUB_FREQUENCY	0x0000000138	32	rwNormal read/write	0x0000000A	Scrub interval
HBMMC_NA1_SCRUB_INIT_EN	0x000000013C	32	rwNormal read/write	0x00000000	Scrubbing and initialization control
HBMMC_NA1_SCRUB_INIT_COMPLETE	0x0000000174	32	roRead-only	0x00000000	Scrub initialization complete
HBMMC_NA1_SCRUB_COUNT	0x0000000178	32	roRead-only	0x00000000	Scrub Count
HBMMC_NA1_HBM_RDPAR_ERR1_LOG1_EHP0	0x000000017C	32	rwNormal read/write	0x00000000	First Parity Error on the Read Data from HBM Memory
HBMMC_NA1_HBM_RDPAR_ERR1_LOG2_EHP0	0x0000000180	32	rwNormal read/write	0x00000000	First Parity Error on the Read Data from HBM Memory
HBMMC_NA1_HBM_RDPAR_ERR2_LOG1_EHP1	0x0000000184	32	rwNormal read/write	0x00000000	Second Parity Error on the Read Data from HBM Memory
HBMMC_NA1_HBM_RDPAR_ERR2_LOG2_EHP1	0x0000000188	32	rwNormal read/write	0x00000000	Second Parity Error on the Read Data from HBM Memory
HBMMC_NA1_DBUF_RDPAR_ERR_LOG_EHP2	0x000000018C	32	rwNormal read/write	0x00000000	Read Data Buffer Parity Error
HBMMC_NA1_HBM_RD_CORR_ECC_ERR_LOG1_EHP3	0x0000000190	32	rwNormal read/write	0x00000000	Correctable ECC Error from HBM Memory
HBMMC_NA1_HBM_RD_CORR_ECC_ERR_LOG2_EHP3	0x0000000194	32	rwNormal read/write	0x00000000	Correctable ECC Error from HBM Memory
HBMMC_NA1_HBM_RD_UNCORR_ECC_ERR_LOG1_EHP4	0x0000000198	32	rwNormal read/write	0x00000000	Uncorrectable ECC Error from HBM Memory
HBMMC_NA1_HBM_RD_UNCORR_ECC_ERR_LOG2_EHP4	0x000000019C	32	rwNormal read/write	0x00000000	Uncorrectable ECC Error from HBM Memory
HBMMC_NA1_HBM_WRPAR_ERR1_LOG1_EHP5	0x00000001A0	32	rwNormal read/write	0x00000000	First Parity Error on the Write Data from HBM Memory
HBMMC_NA1_HBM_WRPAR_ERR1_LOG2_EHP5	0x00000001A4	32	rwNormal read/write	0x00000000	First Parity Error on the Write Data from HBM Memory
HBMMC_NA1_HBM_WRPAR_ERR2_LOG1_EHP6	0x00000001A8	32	rwNormal read/write	0x00000000	Second Parity Error on the Write Data from HBM Memory
HBMMC_NA1_HBM_WRPAR_ERR2_LOG2_EHP6	0x00000001AC	32	rwNormal read/write	0x00000000	Second Parity Error on the Write Data from HBM Memory
HBMMC_NA1_DBUF_WRPAR_ERR_LOG_EHP7	0x00000001B0	32	rwNormal read/write	0x00000000	Write Data Buffer Parity Error
HBMMC_NA1_NA_DATAPOISON_ERR_LOG1_EHP8	0x00000001B4	32	rwNormal read/write	0x00000000	Data Poison
HBMMC_NA1_NA_DATAPOISON_ERR_LOG2_EHP8	0x00000001B8	32	rwNormal read/write	0x00000000	Data Poison
HBMMC_NA1_NA_DATAPOISON_ERR_LOG3_EHP8	0x00000001BC	32	rwNormal read/write	0x00000000	Data Poison
HBMMC_NA1_NA_CMDPOISON_ERR_LOG1_EHP9	0x00000001C0	32	rwNormal read/write	0x00000000	Command Poison
HBMMC_NA1_NA_CMDPOISON_ERR_LOG2_EHP9	0x00000001C4	32	rwNormal read/write	0x00000000	Command Poison
HBMMC_NA1_NA_CMDPOISON_ERR_LOG3_EHP9	0x00000001C8	32	rwNormal read/write	0x00000000	Command Poison
HBMMC_NA1_NA_RDPAR_ERR_LOG_EHP10	0x00000001CC	32	rwNormal read/write	0x00000000	Parity Error between NA Async FIFOs on Read Path
HBMMC_NA1_NA_WRPAR_ERR_LOG_EHP11	0x00000001D0	32	rwNormal read/write	0x00000000	Parity Error between NA Async FIFOs on Write Path
HBMMC_NA1_NA_WR_ECC_ERR_LOG_EHP12	0x00000001D4	32	rwNormal read/write	0x00000000	ECC Error on Rx-ed Data Flit between NMU and NA.
HBMMC_NA1_NA_AXILEN_CHK_ERR_LOG_EHP13	0x00000001D8	32	rwNormal read/write	0x00000000	Number of Data Flits don't match AxLEN or if AXLEN is greater than 15
HBMMC_NA1_NA_UNMAP_FLIT_ERR_LOG_EHP14	0x00000001DC	32	rwNormal read/write	0x00000000	Flit on an umapped VC
HBMMC_NA1_NA_INVLD_WRAP_LEN_ERR_LOG_EHP15	0x00000001E0	32	rwNormal read/write	0x00000000	Invalid Wrap Length for a transaction.
HBMMC_NA1_NA_RESP_CTRL_PAR_ERR_LOG_EHP16	0x00000001E4	32	rwNormal read/write	0x00000000	Parity Error in either the BRESP or the RRESP Control signals
HBMMC_NA1_NA_ING_CRDT_ERR_LOG_EHP17	0x00000001E8	32	rwNormal read/write	0x00000000	NSU advertises 0 credits but it receives flits
HBMMC_NA1_NA_DEST_CHK_ERR_LOG_EHP18	0x00000001EC	32	rwNormal read/write	0x00000000	Destination Check mismatch at the NPP Port
HBMMC_NA1_NA_CRDT_RDY_CHK_ERR_LOG_EHP19	0x00000001F0	32	rwNormal read/write	0x00000000	NSU receives a credits when it's credit ready is de-asserted
HBMMC_NA1_NA_CMD_UC_HDR_ERR_LOG_EHP20	0x00000001F4	32	rwNormal read/write	0x00000000	Uncorrectable Error on the Header of a transaction on NPP
HBMMC_NA1_NA_CMD_PAR_ERR_LOG_EHP21	0x00000001F8	32	rwNormal read/write	0x00000000	Parity Error detected on command FIFO in NSU MC
HBMMC_NA1_NA_XMPU_ERR_LOG_EHP22	0x00000001FC	32	rwNormal read/write	0x00000000	XMPU Violation occurred
HBMMC_NA1_HBM_AERR_ERR_LOG_EHP23	0x0000000200	32	rwNormal read/write	0x00000000	AERR error
HBMMC_NA1_HBM_CATTRIP_ERR_LOG_EHP24	0x0000000204	32	rwNormal read/write	0x00000000	CATTRIP error
HBMMC_NA1_NA_CORR_ECC_ERR_LOG_EHP33	0x000000020C	32	rwNormal read/write	0x00000000	Correctable Error on incoming flit of a transaction on NPP
HBMMC_NA1_DPATH_ECC_COUNT	0x00000002C4	32	rwNormal read/write	0x00000000	DPATH Correctable ECC Counter
HBMMC_NA1_NPP_ECC_COUNT_P0	0x00000002C8	32	rwNormal read/write	0x00000000	NSU NPP Correctable ECC Counter Port 0
HBMMC_NA1_NPP_ECC_COUNT_P1	0x00000002CC	32	rwNormal read/write	0x00000000	NSU NPP Correctable ECC Counter Port 1