CAL_SEQUENCE_STATUS_54 (DDRMC_DDR4_XRAM) Register Description
| Register Name | CAL_SEQUENCE_STATUS_54 |
|---|---|
| Offset Address | 0x00000006D8 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Calibration Sequence Status |
64 Register locations containing calibration stage code and status.
CAL_SEQUENCE_STATUS_54 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| cal_stage_status | 8:6 | roRead-only | 0x0 | Calibration Stage status 000: Not started 011: In progress 100: Stage is skipped 110: Stage completed 111: Stage failed |
| cal_stage_code | 5:0 | roRead-only | 0x0 | Calibration Stage Code |