HBMMC_TFAW_S (HBMMC_MC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_TFAW_S (HBMMC_MC) Register Description

Register NameHBMMC_TFAW_S
Offset Address0x0000000124
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x0000000C
DescriptionTFAW Short

HBMMC_TFAW_S (HBMMC_MC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TFAW_S 5:0rwNormal read/write0xCTime specified in HBM memory cycles. Minimum window in which 4 activate commands can be issued to differenct SID rank. Vendor specific option.