REG_PERF_MON_TBASE (NOC_NSU) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_PERF_MON_TBASE (NOC_NSU) Register Description

Register NameREG_PERF_MON_TBASE
Offset Address0x00000001C4
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000003
Descriptionmonitor timebase selection index

REG_PERF_MON_TBASE (NOC_NSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
tslide_lsb 7:3rwNormal read/write0x0Time Slide Window LSB (0-27). This set the latency unit to be 2lsb noc_clk cycles.
sel 2:0rwNormal read/write0x3timebase selection index (0~5)