reg_adec15 (DDRMC_NOC) Register Description
| Register Name | reg_adec15 |
|---|---|
| Offset Address | 0x0000000728 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Address for DRAM ECC error injection. When injection is enabled a write transaction with an address that matches the row, column, bank, group, lrank, and rank match fields will be flagged for error injection. Address bits that are masked off are not considered in the matching logic. |
reg_adec15 (DDRMC_NOC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| match_en | 8 | rwNormal read/write | 0x0 | DRAM ECC error injection enable bit for both persistent and single modes. 0: disable 1: enable |
| done | 7 | rwNormal read/write | 0x0 | DRAM ECC error injection Done bit. HW will set this bit when one or more errors is injected in single or persistent mode. SW must clear this bit to enable error injection in single mode. |
| persistent | 6 | rwNormal read/write | 0x0 | Mode for DRAM ECC error injection. 1: persistent - Errors injected on all address mask/match hits when match_en=0x1. 0: single - One error injected on address mask/match hit when match_en=0x1 and done=0x0. |
| ch_match | 5 | rwNormal read/write | 0x0 | DRAM ECC error injection logical channel match. |
| lrank_match | 4:2 | rwNormal read/write | 0x0 | DRAM ECC error injection logical rank address match. |
| rank_match | 1:0 | rwNormal read/write | 0x0 | DRAM ECC error injection rank address match. |