reg_adec10 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

reg_adec10 (DDRMC_NOC) Register Description

Register Namereg_adec10
Offset Address0x000000005C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Decode

reg_adec10 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bank_029:24rwNormal read/write0x0Memory controller address bit select for bank bit 0
col_923:18rwNormal read/write0x0Memory controller address bit select for column bit 9
col_817:12rwNormal read/write0x0Memory controller address bit select for column bit 8
col_711:6rwNormal read/write0x0Memory controller address bit select for column bit 7
col_6 5:0rwNormal read/write0x0Memory controller address bit select for column bit 6