HBMMC_NA0_NA_CRDT_RDY_CHK_ERR_LOG_EHP19 (HBMMC_NA0) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA0_NA_CRDT_RDY_CHK_ERR_LOG_EHP19 (HBMMC_NA0) Register Description

Register NameHBMMC_NA0_NA_CRDT_RDY_CHK_ERR_LOG_EHP19
Offset Address0x00000001F0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionNSU receives a credits when it's credit ready is de-asserted

HBMMC_NA0_NA_CRDT_RDY_CHK_ERR_LOG_EHP19 (HBMMC_NA0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PORT1 1rwNormal read/write0x0If set indicates that error occurred on NPP Port1, else error occurred on Port0
ERR_VALID 0rwNormal read/write0x0If set indicates HBM controllers NSU egress port receives a credit return when it is not ready to receive