dc0_perf_mon (DDRMC_MAIN) Register Description
| Register Name | dc0_perf_mon |
|---|---|
| Offset Address | 0x00000013C0 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0000003E |
| Description | DC monitor channel 0 |
dc0_perf_mon (DDRMC_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| sngl | 17 | rwNormal read/write | 0x0 | This bit controls the enabling of performance counter captures based on the enable bit only. If this bit is set to 1 the performance monitorring starts when enable is set to 1, and ends when enable is set to 0. The accum_period value is ignored, for performance monitor captures, when this bit is set to 1: 0: disable 1: enable |
| num_ro_of | 16 | rwNormal read/write | 0x0 | When set this bit indicates the roll-over counter has overflowed. Software should clear this field when enabling the performance monitor. |
| num_ro | 15:6 | rwNormal read/write | 0x0 | Number of times the accumulation period has rolled over since the monitor was enabled. Software should clear this field when enabling the performance monitor. |
| accum_period | 5:1 | rwNormal read/write | 0x1F | These bits control the performance monitor accumulation period. The period is set as 2**n * MC clock period divided by 2, where n is the value in this field. The period set here should be fairly large (i.e. usecs). |
| enable | 0 | rwNormal read/write | 0x0 | 0: Channel 0 perf mon disabled 1: Channel 0 perf mon enabled |