HBMMC_NA0_NA_AXILEN_CHK_ERR_LOG_EHP13 (HBMMC_NA0) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA0_NA_AXILEN_CHK_ERR_LOG_EHP13 (HBMMC_NA0) Register Description

Register NameHBMMC_NA0_NA_AXILEN_CHK_ERR_LOG_EHP13
Offset Address0x00000001D8
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionNumber of Data Flits don't match AxLEN or if AXLEN is greater than 15

HBMMC_NA0_NA_AXILEN_CHK_ERR_LOG_EHP13 (HBMMC_NA0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PORT129rwNormal read/write0x0If set indicates that error occurred on NPP Port1, else error occurred on Port0
AXLEN28:21rwNormal read/write0x0Logs the AXLEN of the transaction
TAG20:13rwNormal read/write0x0Logs the TAG of the transaction
SRC_ID12:1rwNormal read/write0x0Logs the SOURCE ID of the transaction
ERR_VALID 0rwNormal read/write0x0If set indicates AXI length on the header flit is greater than 15, or in a write transaction, the number of write data flits does not match the AXI length