F0_CALBISC_RL_DLY_QTR_13 (DDRMC_LPDDR4_XRAM) Register Description
| Register Name | F0_CALBISC_RL_DLY_QTR_13 |
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| Offset Address | 0x0000002034 |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | BISC RL_DLY_QTR value during F0 calibration |
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Number of read delay taps equivalent to 1/4 tCK. Permuted by nibbles.
F0_CALBISC_RL_DLY_QTR_13 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Value | 8:0 | roRead-only | 0x0 | BISC RL_DLY_QTR |