LPQDQSOSCTRACK_WLDLYRNK0_FINE_MIN_13 (DDRMC_LPDDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

LPQDQSOSCTRACK_WLDLYRNK0_FINE_MIN_13 (DDRMC_LPDDR4_XRAM) Register Description

Register NameLPQDQSOSCTRACK_WLDLYRNK0_FINE_MIN_13
Offset Address0x00000049EC
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionLP4 Oscillator Tracking, Rank 0 Fine Taps, Min

Smallest value of fine taps for each nibble for Rank 0 since calibration completed. Permuted by nibbles.

LPQDQSOSCTRACK_WLDLYRNK0_FINE_MIN_13 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0LP4 Oscillator Tracking, Rank 0 Fine Taps, Min