F0_DQSGATE_STG1_RLDLYRANK_CRSE_62 (DDRMC_DDR4_XRAM) Register Description
Register Name | F0_DQSGATE_STG1_RLDLYRANK_CRSE_62 |
Offset Address | 0x0000002360 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | DQSGate Stage 1 RLDelay Rank Coarse |
DQS Gate calibration stage: Coarse tap value for the 3rd DQS edge. Permuted by byte lanes and ranks.
F0_DQSGATE_STG1_RLDLYRANK_CRSE_62 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | DQSGate Stage 1 RLDelay Rank Coarse |