HBMMC_NA1_HBM_WRPAR_ERR1_LOG2_EHP5 (HBMMC_NA1) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA1_HBM_WRPAR_ERR1_LOG2_EHP5 (HBMMC_NA1) Register Description

Register NameHBMMC_NA1_HBM_WRPAR_ERR1_LOG2_EHP5
Offset Address0x00000001A4
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionFirst Parity Error on the Write Data from HBM Memory

HBMMC_NA1_HBM_WRPAR_ERR1_LOG2_EHP5 (HBMMC_NA1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
COL20:16rwNormal read/write0x0Logs the COL Address of the transaction
ROW15:0rwNormal read/write0x0Logs the ROW Address of the transaction