HBMMC_NA1_NA_WRPAR_ERR_LOG_EHP11 (HBMMC_NA1) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA1_NA_WRPAR_ERR_LOG_EHP11 (HBMMC_NA1) Register Description

Register NameHBMMC_NA1_NA_WRPAR_ERR_LOG_EHP11
Offset Address0x00000001D0
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionParity Error between NA Async FIFOs on Write Path

HBMMC_NA1_NA_WRPAR_ERR_LOG_EHP11 (HBMMC_NA1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PORT125rwNormal read/write0x0If set indicates that error occurred on NPP Port1, else error occurred on Port0
FIFO_POP_ADDR24:21rwNormal read/write0x0Logs the Pop ADDRESS of the NA Async FIFO with Parity Error
TAG20:13rwNormal read/write0x0Logs the TAG of the transaction
SRC_ID12:1rwNormal read/write0x0Logs the SOURCE ID of the transaction
ERR_VALID 0rwNormal read/write0x0If set indicates parity error found on data pulled from the asynchronous write data FIFO