dc_eccw_data_par_err_log0_1 (DDRMC_MAIN) Register Description
| Register Name | dc_eccw_data_par_err_log0_1 |
|---|---|
| Offset Address | 0x00000013B4 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Channel 1 DC ECCW data parity error log0 |
dc_eccw_data_par_err_log0_1 (DDRMC_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| err_log_info | 31:0 | rwNormal read/write | 0x0 | error log info for DC DBUF to ECCW path [4:0]: transaction queue address id [20:5]: ECCW data parity error [22:21]: data chunk [30:23]: N/A [31]: error log valid bit |