HBMMC_NA1_JEDEC_DEVICE_CODE (HBMMC_NA1) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_NA1_JEDEC_DEVICE_CODE (HBMMC_NA1) Register Description

Register NameHBMMC_NA1_JEDEC_DEVICE_CODE
Offset Address0x0000000128
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x0000000A
DescriptionHBM Device JEDEC Density Code

HBMMC_NA1_JEDEC_DEVICE_CODE (HBMMC_NA1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
OFFSET_128M12:4rwNormal read/write0x0128MB base address offset,
supports remapped non-power of 2 memory sizes
For interleaved memory, offsets should be multiplied by interleave factor. For example, an offset of 6 must be programmed as 6x4=24 of a 4-way interleave configuration.
DENSITY_CODE 3:0rwNormal read/write0xADENSITY_CODE:
4H: JEDEC Density Code = 4b0011 -> RA[13:0], BA[3:0], CA[5:1]
4H: JEDEC Density Code = 4b0110 -> RA[14:0], BA[3:0], CA[5:1]
8H: JEDEC Density Code = 4b0100 -> RA[13:0], S[0], BA[3:0], CA[5:1]
8H: JEDEC Density Code = 4b1000 -> RA[14:0], S[0], BA[3:0], CA[5:1] //RA[14:13] = 2b11 is invalid
8H: JEDEC Density Code = 4b1010 -> RA[14:0], S[0], BA[3:0], CA[5:1]