nsu1_perf_mon_1_2 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu1_perf_mon_1_2 (DDRMC_NOC) Register Description

Register Namensu1_perf_mon_1_2
Offset Address0x0000000554
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionTransaction count NSU1

nsu1_perf_mon_1_2 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
header_ovf31roRead-only0x0Header count overflow
header30:0roRead-only0x0Accumulated NoC header flits within a time slot