REG_4 (CMT_XPLL) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)
Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_4 (CMT_XPLL) Register Description

Register NameREG_4
Offset Address0x0000000038
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000A00
DescriptionREG_4

REG_4 (CMT_XPLL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0for prediv2
CLKOUT0_P5_FEDGE15rwNormal read/write0x0for prediv2
CLKOUT0_START_H14rwNormal read/write0x0for prediv2
CLKOUT0_P5EN13rwNormal read/write0x0for prediv2
clkout0_USED12rwNormal read/write0x0TRUE: The pre-divide of 2 is enabled
CLKOUT0_PREDIV211rwNormal read/write0x1TRUE: The pre-divide of 2 is enabled
CLKOUT0_MX10:9rwNormal read/write0x1XPLL O0 counter clock input mux control
CLKOUT0_EDGE 8rwNormal read/write0x0XPLL O0 counter high to low clock edge transition control
CLKOUT0_DT 7:0rwNormal read/write0x0XPLL O0 counter delay setting