REG_1ST_ERR_INFO_5 (NOC_NMU_HBM2E) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_1ST_ERR_INFO_5 (NOC_NMU_HBM2E) Register Description

Register NameREG_1ST_ERR_INFO_5
Offset Address0x000000082C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionNoC First Error Information

REG_1ST_ERR_INFO_5 (NOC_NMU_HBM2E) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_l31:0roRead-only0x0AXI address lower 32-bit