F0_WRLAT_PHY_OE_NIB_FINAL_4 (DDRMC_DDR4_XRAM) Register Description
| Register Name | F0_WRLAT_PHY_OE_NIB_FINAL_4 |
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| Offset Address | 0x0000003F04 |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | WRLAT Final Output Enable Latency |
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Write Latency Calibration Stage: Final Output Enable latency. Permuted by byte lanes.
F0_WRLAT_PHY_OE_NIB_FINAL_4 (DDRMC_DDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Value | 8:0 | roRead-only | 0x0 | WRLAT Final Output Enable Latency |