DDRMC_NOC Module

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID

AM019

Release Date

2023-11-17

Revision

1.1

DDRMC_NOC Module Description

Module Name	DDRMC_NOC Module
Base Addresses	This module description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Description	DDRMC NoC Interface Control and Status

DDRMC_NOC Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
pcsr_lock	0x000000000C	32	rwNormal read/write	0x00000001	NPI Lock Register
reg_adec4	0x0000000044	32	rwNormal read/write	0x00000000	Address Decode
reg_adec5	0x0000000048	32	rwNormal read/write	0x00000000	Address Decode
reg_adec6	0x000000004C	32	rwNormal read/write	0x00000000	Address Decode
reg_adec7	0x0000000050	32	rwNormal read/write	0x00000000	Address Decode
reg_adec8	0x0000000054	32	rwNormal read/write	0x00000000	Address Decode
reg_adec9	0x0000000058	32	rwNormal read/write	0x00000000	Address Decode
reg_adec10	0x000000005C	32	rwNormal read/write	0x00000000	Address Decode
reg_adec11	0x0000000060	32	rwNormal read/write	0x00000000	Address Decode
reg_qos_timeout0	0x000000044C	32	rwNormal read/write	0x01084210	QoS Timeout Scale Factor Control
reg_qos_timeout1	0x0000000450	32	rwNormal read/write	0xFFFFFFFF	QoS Starvation
reg_qos_timeout2	0x0000000454	32	rwNormal read/write	0x000000FF	QoS Starvation
perf_mon_timebase_scale	0x00000004D4	32	rwNormal read/write	0x000BDEF7	Performance monitor measurement Interval
nsu0_perf_mon_ctl_0_0	0x00000004D8	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU0
nsu0_perf_mon_ctl_0_1	0x00000004DC	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU0
nsu0_perf_filter_0_0	0x00000004E0	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU0
nsu0_perf_filter_0_1	0x00000004E4	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU0
nsu0_perf_filter_en_0	0x00000004E8	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 enable NSU0
nsu0_perf_mon_0_0	0x00000004EC	32	roRead-only	0x00000000	Accumulated Latency NSU0
nsu0_perf_mon_0_1	0x00000004F0	32	roRead-only	0x00000000	Burst count NSU0
nsu0_perf_mon_0_2	0x00000004F4	32	roRead-only	0x00000000	Transaction count NSU0
nsu0_perf_mon_ctl_1_0	0x00000004F8	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU0
nsu0_perf_mon_ctl_1_1	0x00000004FC	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU0
nsu0_perf_filter_1_0	0x0000000500	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU0
nsu0_perf_filter_1_1	0x0000000504	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU0
nsu0_perf_filter_en_1	0x0000000508	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 enable NSU0
nsu0_perf_mon_1_0	0x000000050C	32	roRead-only	0x00000000	Accumulated Latency NSU0
nsu0_perf_mon_1_1	0x0000000510	32	roRead-only	0x00000000	Burst count NSU0
nsu0_perf_mon_1_2	0x0000000514	32	roRead-only	0x00000000	Transaction count NSU0
nsu1_perf_mon_ctl_0_0	0x0000000518	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU1
nsu1_perf_mon_ctl_0_1	0x000000051C	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU1
nsu1_perf_filter_0_0	0x0000000520	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU1
nsu1_perf_filter_0_1	0x0000000524	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU1
nsu1_perf_filter_en_0	0x0000000528	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 enable NSU1
nsu1_perf_mon_0_0	0x000000052C	32	roRead-only	0x00000000	Accumulated Latency NSU1
nsu1_perf_mon_0_1	0x0000000530	32	roRead-only	0x00000000	Burst count NSU1
nsu1_perf_mon_0_2	0x0000000534	32	roRead-only	0x00000000	Transaction count NSU1
nsu1_perf_mon_ctl_1_0	0x0000000538	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU1
nsu1_perf_mon_ctl_1_1	0x000000053C	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU1
nsu1_perf_filter_1_0	0x0000000540	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU1
nsu1_perf_filter_1_1	0x0000000544	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU1
nsu1_perf_filter_en_1	0x0000000548	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 enable NSU1
nsu1_perf_mon_1_0	0x000000054C	32	roRead-only	0x00000000	Accumulated Latency NSU1
nsu1_perf_mon_1_1	0x0000000550	32	roRead-only	0x00000000	Burst count NSU1
nsu1_perf_mon_1_2	0x0000000554	32	roRead-only	0x00000000	Transaction count NSU1
nsu2_perf_mon_ctl_0_0	0x0000000558	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU2
nsu2_perf_mon_ctl_0_1	0x000000055C	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU2
nsu2_perf_filter_0_0	0x0000000560	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU2
nsu2_perf_filter_0_1	0x0000000564	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU2
nsu2_perf_filter_en_0	0x0000000568	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 enable NSU2
nsu2_perf_mon_0_0	0x000000056C	32	roRead-only	0x00000000	Accumulated Latency NSU2
nsu2_perf_mon_0_1	0x0000000570	32	roRead-only	0x00000000	Burst count NSU2
nsu2_perf_mon_0_2	0x0000000574	32	roRead-only	0x00000000	Transaction count NSU2
nsu2_perf_mon_ctl_1_0	0x0000000578	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU2
nsu2_perf_mon_ctl_1_1	0x000000057C	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU2
nsu2_perf_filter_1_0	0x0000000580	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU2
nsu2_perf_filter_1_1	0x0000000584	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU2
nsu2_perf_filter_en_1	0x0000000588	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 enable NSU2
nsu2_perf_mon_1_0	0x000000058C	32	roRead-only	0x00000000	Accumulated Latency NSU2
nsu2_perf_mon_1_1	0x0000000590	32	roRead-only	0x00000000	Burst count NSU2
nsu2_perf_mon_1_2	0x0000000594	32	roRead-only	0x00000000	Transaction count NSU2
nsu3_perf_mon_ctl_0_0	0x0000000598	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU3
nsu3_perf_mon_ctl_0_1	0x000000059C	32	rwNormal read/write	0x00000000	Performance monitor 0 control NSU3
nsu3_perf_filter_0_0	0x00000005A0	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU3
nsu3_perf_filter_0_1	0x00000005A4	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 NSU3
nsu3_perf_filter_en_0	0x00000005A8	32	rwNormal read/write	0x00000000	Performance monitor filter set 0 enable NSU3
nsu3_perf_mon_0_0	0x00000005AC	32	roRead-only	0x00000000	Accumulated Latency NSU3
nsu3_perf_mon_0_1	0x00000005B0	32	roRead-only	0x00000000	Burst count NSU3
nsu3_perf_mon_0_2	0x00000005B4	32	roRead-only	0x00000000	Transaction count NSU3
nsu3_perf_mon_ctl_1_0	0x00000005B8	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU3
nsu3_perf_mon_ctl_1_1	0x00000005BC	32	rwNormal read/write	0x00000000	Performance monitor 1 control NSU3
nsu3_perf_filter_1_0	0x00000005C0	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU3
nsu3_perf_filter_1_1	0x00000005C4	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 NSU3
nsu3_perf_filter_en_1	0x00000005C8	32	rwNormal read/write	0x00000000	Performance monitor filter set 1 enable NSU3
nsu3_perf_mon_1_0	0x00000005CC	32	roRead-only	0x00000000	Accumulated Latency NSU3
nsu3_perf_mon_1_1	0x00000005D0	32	roRead-only	0x00000000	Burst count NSU3
nsu3_perf_mon_1_2	0x00000005D4	32	roRead-only	0x00000000	Transaction count NSU3
nsu0_err_log0_en	0x00000005D8	32	rwNormal read/write	0x00001FFF	Error logging and ISR generation enable for nsu0 ISR bit 0
nsu0_err_log1_en	0x00000005DC	32	rwNormal read/write	0x0107E000	Error logging and ISR generation enable for nsu0 ISR bit 1
nsu0_err_status	0x00000005E0	32	wtcReadable, write a 1 to clear	0x00000000	Sticky error detector status. HW sets these bits if the corresponding error has ever been detected.
nsu0_err_log0_0	0x00000005E4	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log0_1	0x00000005E8	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log0_2	0x00000005EC	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log0_3	0x00000005F0	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log0_4	0x00000005F4	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log1_0	0x00000005F8	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log1_1	0x00000005FC	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log1_2	0x0000000600	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log1_3	0x0000000604	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu0_err_log1_4	0x0000000608	32	roRead-only	0x00000000	NSU0 non-fatal error log
nsu1_err_log0_en	0x000000060C	32	rwNormal read/write	0x00001FFF	Error logging and ISR generation enable for nsu1 ISR bit 0
nsu1_err_log1_en	0x0000000610	32	rwNormal read/write	0x0107E000	Error logging and ISR generation enable for nsu1 ISR bit 1
nsu1_err_status	0x0000000614	32	wtcReadable, write a 1 to clear	0x00000000	Sticky error detector status. HW sets these bits if the corresponding error has ever been detected.
nsu1_err_log0_0	0x0000000618	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log0_1	0x000000061C	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log0_2	0x0000000620	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log0_3	0x0000000624	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log0_4	0x0000000628	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log1_0	0x000000062C	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log1_1	0x0000000630	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log1_2	0x0000000634	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log1_3	0x0000000638	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu1_err_log1_4	0x000000063C	32	roRead-only	0x00000000	NSU1 non-fatal error log
nsu2_err_log0_en	0x0000000640	32	rwNormal read/write	0x00001FFF	Error logging and ISR generation enable for nsu2 ISR bit 0
nsu2_err_log1_en	0x0000000644	32	rwNormal read/write	0x0107E000	Error logging and ISR generation enable for nsu2 ISR bit 1
nsu2_err_status	0x0000000648	32	wtcReadable, write a 1 to clear	0x00000000	Sticky error detector status. HW sets these bits if the corresponding error has ever been detected.
nsu2_err_log0_0	0x000000064C	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log0_1	0x0000000650	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log0_2	0x0000000654	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log0_3	0x0000000658	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log0_4	0x000000065C	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log1_0	0x0000000660	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log1_1	0x0000000664	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log1_2	0x0000000668	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log1_3	0x000000066C	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu2_err_log1_4	0x0000000670	32	roRead-only	0x00000000	NSU2 non-fatal error log
nsu3_err_log0_en	0x0000000674	32	rwNormal read/write	0x00001FFF	Error logging and ISR generation enable for nsu3 ISR bit 0
nsu3_err_log1_en	0x0000000678	32	rwNormal read/write	0x0107E000	Error logging and ISR generation enable for nsu3 ISR bit 1
nsu3_err_status	0x000000067C	32	wtcReadable, write a 1 to clear	0x00000000	Sticky error detector status. HW sets these bits if the corresponding error has ever been detected.
nsu3_err_log0_0	0x0000000680	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log0_1	0x0000000684	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log0_2	0x0000000688	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log0_3	0x000000068C	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log0_4	0x0000000690	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log1_0	0x0000000694	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log1_1	0x0000000698	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log1_2	0x000000069C	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log1_3	0x00000006A0	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu3_err_log1_4	0x00000006A4	32	roRead-only	0x00000000	NSU3 non-fatal error log
nsu0_err_ctrl	0x00000006A8	32	rwNormal read/write	0x00003000	Error Control
nsu1_err_ctrl	0x00000006AC	32	rwNormal read/write	0x00003000	Error Control
nsu2_err_ctrl	0x00000006B0	32	rwNormal read/write	0x00003000	Error Control
nsu3_err_ctrl	0x00000006B4	32	rwNormal read/write	0x00003000	Error Control
ecc_err_inj_nsu0	0x00000006B8	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
ecc_err_inj_nsu1	0x00000006BC	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
ecc_err_inj_nsu2	0x00000006C0	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
ecc_err_inj_nsu3	0x00000006C4	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
na_err_ctrl_0	0x0000000710	32	rwNormal read/write	0x10000000	Flips corresponding egress ECC and/or parity bit.
na_err_ctrl_1	0x0000000714	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
na_err_ctrl_3	0x0000000718	32	rwNormal read/write	0x00000000	Flips corresponding egress ECC and/or parity bit.
reg_adec12	0x000000071C	32	rwNormal read/write	0x00000000	Address mask for DRAM ECC Error Injection
reg_adec13	0x0000000720	32	rwNormal read/write	0x00000000	Address mask for DRAM ECC Error Injection
reg_adec14	0x0000000724	32	rwNormal read/write	0x00000000	Address for DRAM ECC error injection. When injection is enabled a write transaction with an address that matches the row, column, bank, group, lrank, and rank match fields will be flagged for error injection. Address bits that are masked off are not considered in the matching logic.
reg_adec15	0x0000000728	32	rwNormal read/write	0x00000000	Address for DRAM ECC error injection. When injection is enabled a write transaction with an address that matches the row, column, bank, group, lrank, and rank match fields will be flagged for error injection. Address bits that are masked off are not considered in the matching logic.
add_par_err_inj_adec	0x000000072C	32	rwNormal read/write	0x0003C000	Flips DDR4 DRAM address parity bit, parity check and log enables in ADEC.
adec_add_par_err_log0_0	0x0000000730	32	rwNormal read/write	0x00000000	Channel 0 ADEC address parity error log0
adec_add_par_err_log1_0	0x0000000734	32	rwNormal read/write	0x00000000	Channel 0 ADEC address parity error log1
adec_add_par_err_log0_1	0x0000000738	32	rwNormal read/write	0x00000000	Channel 1 ADEC address parity error log0
adec_add_par_err_log1_1	0x000000073C	32	rwNormal read/write	0x00000000	Channel 1 ADEC address parity error log1
xmpu_ctrl	0x0000010000	32	mixedMixed types. See bit-field details.	0x0000000B	XMPU ctrl
xmpu_err_status	0x0000010004	32	mixedMixed types. See bit-field details.	0x00000000	XMPU error status
xmpu_err_add_lo0	0x0000010008	32	rwNormal read/write	0x00000000	XMPU error address lower
xmpu_err_add_hi0	0x000001000C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU error address higher
xmpu_err_axi_id	0x0000010010	32	mixedMixed types. See bit-field details.	0x00000000	XMPU error id
xmpu_lock	0x0000010020	1	rwsoRead/write, set only	0x00000000	Write Protect Register
xmpu_start_lo0	0x0000010100	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi0	0x0000010104	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo0	0x0000010108	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi0	0x000001010C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master0	0x0000010110	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config0	0x0000010114	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo1	0x0000010118	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi1	0x000001011C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo1	0x0000010120	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi1	0x0000010124	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master1	0x0000010128	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config1	0x000001012C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo2	0x0000010130	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi2	0x0000010134	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo2	0x0000010138	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi2	0x000001013C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master2	0x0000010140	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config2	0x0000010144	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo3	0x0000010148	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi3	0x000001014C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo3	0x0000010150	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi3	0x0000010154	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master3	0x0000010158	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config3	0x000001015C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo4	0x0000010160	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi4	0x0000010164	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo4	0x0000010168	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi4	0x000001016C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master4	0x0000010170	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config4	0x0000010174	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo5	0x0000010178	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi5	0x000001017C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo5	0x0000010180	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi5	0x0000010184	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master5	0x0000010188	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config5	0x000001018C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo6	0x0000010190	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi6	0x0000010194	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo6	0x0000010198	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi6	0x000001019C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master6	0x00000101A0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config6	0x00000101A4	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo7	0x00000101A8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi7	0x00000101AC	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo7	0x00000101B0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi7	0x00000101B4	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master7	0x00000101B8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config7	0x00000101BC	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo8	0x00000101C0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi8	0x00000101C4	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo8	0x00000101C8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi8	0x00000101CC	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master8	0x00000101D0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config8	0x00000101D4	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo9	0x00000101D8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi9	0x00000101DC	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo9	0x00000101E0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi9	0x00000101E4	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master9	0x00000101E8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config9	0x00000101EC	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo10	0x00000101F0	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi10	0x00000101F4	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo10	0x00000101F8	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi10	0x00000101FC	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master10	0x0000010200	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config10	0x0000010204	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo11	0x0000010208	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi11	0x000001020C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo11	0x0000010210	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi11	0x0000010214	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master11	0x0000010218	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config11	0x000001021C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo12	0x0000010220	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi12	0x0000010224	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo12	0x0000010228	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi12	0x000001022C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master12	0x0000010230	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config12	0x0000010234	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo13	0x0000010238	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi13	0x000001023C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo13	0x0000010240	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi13	0x0000010244	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master13	0x0000010248	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config13	0x000001024C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo14	0x0000010250	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi14	0x0000010254	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo14	0x0000010258	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi14	0x000001025C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master14	0x0000010260	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config14	0x0000010264	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config
xmpu_start_lo15	0x0000010268	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, lower portion
xmpu_start_hi15	0x000001026C	32	mixedMixed types. See bit-field details.	0x00000000	XMPU start address, upper portion
xmpu_end_lo15	0x0000010270	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, lower portion
xmpu_end_hi15	0x0000010274	32	mixedMixed types. See bit-field details.	0x00000000	XMPU end address, upper portion
xmpu_master15	0x0000010278	32	mixedMixed types. See bit-field details.	0x00000000	XMPU master ID and mask
xmpu_config15	0x000001027C	32	mixedMixed types. See bit-field details.	0x00000008	XMPU entry config