HBMMC_IDLE_TIMEOUT (HBMMC_MC) Register Description
| Register Name | HBMMC_IDLE_TIMEOUT |
|---|---|
| Offset Address | 0x00000001B8 |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00001000 |
| Description | Channel Idle Timeout to SR or PD |
HBMMC_IDLE_TIMEOUT (HBMMC_MC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| T_IDLE_ITVL | 26:0 | rwNormal read/write | 0x1000 | Time specified in MC clock cycles. PowerDown: if enabled - t_idle_itvl cycle delay from last received command received in transaction queue until powerdown state entered. SelfRefresh: If enabled - {1X,2X, 4X or 8X} t_idle_itvl delay from last received command received in transaction queue. |