nsu2_perf_mon_0_0 (DDRMC_NOC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

nsu2_perf_mon_0_0 (DDRMC_NOC) Register Description

Register Namensu2_perf_mon_0_0
Offset Address0x000000056C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAccumulated Latency NSU2

nsu2_perf_mon_0_0 (DDRMC_NOC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
lat_ovf31roRead-only0x0Latency overflow
lat30:0roRead-only0x0Accumulated Average Latency".
Response timestamp minus Header timestamp within a time slot.