F0_RDCMPLX_PQTR_FINAL_17 (DDRMC_LPDDR4_XRAM) Register Description
Register Name | F0_RDCMPLX_PQTR_FINAL_17 |
Offset Address | 0x0000004400 |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | RDComplex Rising Final |
Read Complex Calibration Stage: Final centered tap value for rising clock. Permuted by nibbles.
F0_RDCMPLX_PQTR_FINAL_17 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | RDComplex Rising Final |