HBMMC_TCCD_L (HBMMC_MC) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

HBMMC_TCCD_L (HBMMC_MC) Register Description

Register NameHBMMC_TCCD_L
Offset Address0x0000000158
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperwNormal read/write
Reset Value0x00000004
DescriptionTCCD Long

HBMMC_TCCD_L (HBMMC_MC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TCCD_L 5:0rwNormal read/write0x4Time specified in HBM memory cycles. Minimum from Command to Command to same bank group