REG_PERF_MON0_LATENCY_ACC_LWR (NOC_NMU) Register Description
| Register Name | REG_PERF_MON0_LATENCY_ACC_LWR |
|---|---|
| Offset Address | 0x000000087C |
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Monitor-0 Accumulated latency (lower part) |
REG_PERF_MON0_LATENCY_ACC_LWR (NOC_NMU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| nmu | 31:0 | rwNormal read/write | 0x0 | Accumulated latency lower 32-bits (see tslide_lsb for unit) |