F0_WRDQDBI_RIGHT_MARGIN_5 (DDRMC_LPDDR4_XRAM) Register Description
| Register Name | F0_WRDQDBI_RIGHT_MARGIN_5 |
|---|
| Offset Address | 0x0000003C04 |
|---|
| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
|---|
| Width | 32 |
|---|
| Type | roRead-only |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | WRDQDBI Right Margin |
|---|
Write DQ/DBI Deskew Calibration stage: Smallest margin right of center for the byte in Odelay taps. Permuted by byte lanes.
F0_WRDQDBI_RIGHT_MARGIN_5 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Value | 8:0 | roRead-only | 0x0 | WRDQDBI Right Margin |