F0_WRDQDBI_STG3_DQ_ODLY_1 (DDRMC_LPDDR4_XRAM) Register Description
Register Name | F0_WRDQDBI_STG3_DQ_ODLY_1 |
Offset Address | 0x00000035BC |
Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
|
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | WRDQDBI Stage 3 DQ Odelay |
Write DQ/DBI Deskew Calibration stage: Odelay value for the valid window using DQ delay. Permuted by DQ bits.
F0_WRDQDBI_STG3_DQ_ODLY_1 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Value | 8:0 | roRead-only | 0x0 | WRDQDBI Stage 3 DQ Odelay |