Upgrading in the Vivado Design Suite

Upgrading in the Vivado Design Suite - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID

PG047

Release Date

2023-11-01

Version

16.2 English

This section provides information about any changes to the user logic or port designations that take place when you upgrade to a more current version of this IP core in the AMD Vivado™ Design Suite.

Table 1. Ports Added in V16.1
In/Out	Port Name	Description	What to do
Out	`gtpowergood`	See UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for AMD UltraScale™ and AMD UltraScale+™ usage guidelines of the signal.	Port is useful in AMD UltraScale+™ device families when using `gtrefclk` for other applications.

Table 2. Parameters Added in V16.0
Generic Name	Applicability	Description	Values
InstantiateBitslice0	Applicable in Asynchronous 1000BASE-X/SGMII mode only	This indicates whether to instantiate BITSLICE0 if BITSLICE0 of RX_NIBBLE is unused.	True False
RxNibbleBitslice0Used	Applicable in Asynchronous 1000BASE-X/SGMII mode only	This is an indication to the core if the BITSLICE0 of RX_NIBBLE is used for the clock.	True False
ClockSelection	Applicable in Asynchronous 1000BASE-X/SGMII mode only	This is applicable only when SGMII is selected as physical interface. Setting TRUE enables options for setting reference clock frequencies.	Sync Async

Table 3. Ports Added in V16.0
In/Out	Port Name	Description	What to do
In	tx_dly_rdy_n¹	TX delay ready from adjacent BYTE_GROUPs	For multiple core instantiations connect to the appropriate port in the instance without Shared Logic in the Core.
In	rx_dly_rdy_n¹	RX delay ready from adjacent BYTE_GROUPs
In	tx_vtc_rdy_n¹	TX VTC ready from adjacent BYTE_GROUPs
In	rx_vtc_rdy_n¹	RX VTC ready from adjacent BYTE_GROUPs
n=1, 2, 3.