Reset Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English
Table 1. Reset Signals Pinout
Signal Direction Clock Domain Description
reset Input n/a Asynchronous reset for the entire core. Active-High
resetdone Input userclk Marks the completion of the gtwizard reset sequence. In cases where the transceiver is not present, this signal is tied to 1.