Transceiver Wrapper - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This device-specific transceiver wrapper is instantiated from the block-level HDL file of the example design and is described in the following files:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ synth/transceiver/<component_name>_transceiver.v[hd]

This file instances output source files from the transceiver wizard (used with Gigabit Ethernet 1000BASE-X attributes).