The following tables show the physical side interface ports for Asynchronous SGMII over LVDS using Ultrascale Select IO logic or Versal Advanced IO Wizard when the shared logic is included in example design.
| Signal | Direction | Description |
|---|---|---|
| clk125m | Input | 125 MHz Core clock |
| clk312 | Input | 312 MHz Reference clock which is used by the RX Datapath of LVDS Transceiver block |
| tx_bsc_rst | Input | Reset the BITSLICE_CONTROL Primitive controlling the TX Nibble |
| rx_bsc_rst | Input | Reset the BITSLICE_CONTROL Primitive controlling the RX Nibble |
| tx_bs_rst | Input | Reset for TX_BITSLICE primitives used In the TX nibble |
| rx_bs_rst | Input | Reset for RX_BITSLICE primitives used In the RX nibble |
| tx_rst_dly | Input | Resets the internal delay lines used by TX_BITSLICE primitives within the TX nibble |
| rx_rst_dly | Input | Resets the internal delay lines used by RX_BITSLICE primitives within the RX nibble |
| tx_rdclk | Input | 156.25 Mhz clock used by TX gearbox whose 8 bit data output is synchronous to this clock |
| tx_pll_clk | Input | PLL clock which is used to clock the Transmit path BITSLICE_CONTROL Primitive |
| rx_pll_clk | Input | PLL clock which is used to clock the Receive path BITSLICE_CONTROL Primitive |
| tx_bsc_en_vtc | Input | Enable Voltage, Temperature and Process compensation for BITSLICE_CONTROL Primitive controlling the TX datapath |
| rx_bsc_en_vtc | Input | Enable Voltage, Temperature and Process compensation for BITSLICE_CONTROL Primitive controlling the TX datapath |
| tx_bs_en_vtc | Input | Enable Voltage, Temperature and Process compensation for TX_BITSLICE primitives |
| rx_btval[8:0] | Input | This value provided by the used is used to calculate the number of taps required to maintain a relative delay of 400 ps between the two RX_BITSLIC primitives |
| tx_dly_ready | Output | Asserted High to indicate that delay line calibration is complete for TX_BITSLICE primitives. |
| rx_dly_ready | Output | Asserted High to indicate that delay line calibration is complete for RX_BITSLICE primitives. |
| tx_vtc_ready | Output | Asserted High to indicate that the TX_BITSLICE primitive is ready for Voltage, Temperature and Process compensation |
| rx_vtc_ready | Output | Asserted High to indicate that the RX_BITSLICE primitive is ready for Voltage, Temperature and Process compensation |
| Signal | Direction | Description |
|---|---|---|
| clk125m | Input | 125 MHz core clock |
| pll_rst_in | Input | XPLL Reset |
| pll_clk_in | Input | XPLL Reference clock |
| ctrl_clk | Input | Reference clock used by the XPHY for RIU interface, Delay lines and Built in Self Calibration (BISC). |
| pll_locked_out | Output | Indicates whether the XPLL is Locked |
| dly_ready | Output | DLY_READY output port of the XPHY primitive. Indicates that delay line values can be changed. |
| vtc_ready | Output | VTC_READY output port of the XPHY primitive. Indicates that XPHY is ready for voltage temperature compensation. |
The following are the physical interface ports when the core is configured with the include shared logic in core option. The below ports are only applicable to Ultrascale and Ultrascale + devices.
| Signal | Direction | Description |
|---|---|---|
| tx_dly_ready<n> | Input | Asserted HIGH if TX nibble Delay line calibration is complete for the nth core instance |
| rx_dly_ready<n> | Input | Asserted HIGH if RX nibble Delay line calibration is complete for the nth core instance |
| tx_vtc_ready<n> | Input | Asserted HIGH if TX nibble of the nth core instance is ready for Voltage, Temperature and Process compensation |
| rx_vtc_ready<n> | Input | Asserted HIGH if RX nibble of the nth core instance is ready for Voltage, Temperature and Process compensation |
| clk312_out | Output | 312Mhz clock that is used by the RX datapath of the LVDS Transceiver block. To be shared with other core instances. |
| clk125_out | Output | 125Mhz Reference clock. To be shared with other core instances. |
| rx_logic_reset | Output | To be combined with tx_logic reset using an OR gate to reset other core instances |
| tx_logic_reset | Output | -- |
| tx_locked | Output | LOCKED output of the PLL that is being used to clock the BISLICE_CONTROL primitives on the TX datapath |
| rx_locked | Output | LOCKED output of the PLL that is being used to clock the BISLICE_CONTROL primitives on the RX datapath |
| tx_bsc_rst_out | Output | To be connected to tx_bsc_rst input port, of cores without shared logic |
| rx_bsc_rst_out | Output | To be connected to rx_bsc_rst input port, of cores without shared logic |
| rx_bs_rst_out | Output | To be connected to rx_bs_rst input port, of cores without shared logic |
| tx_bs_rst_out | Output | To be connected to tx_bs_rst input port, of cores without shared logic |
| tx_rst_dly_out | Output | To be connected to tx_rst_dly input port, of cores without shared logic |
| rx_rst_dly_out | Output | To be connected to rx_rst_dly input port, of cores without shared logic |
| tx_bsc_en_vtc_out | Output | To be connected to tx_bsc_en_vtc input port, of cores without shared logic |
| rx_bsc_en_vtc_out | Output | To be connected to rx_bsc_en_vtc input port, of cores without shared logic |
| tx_bsc_en_vtc_out | Output | To be connected to tx_bsc_en_vtc input port, of cores without shared logic |
| rx_bsc_en_vtc_out | Output | To be connected to rx_bsc_en_vtc input port, of cores without shared logic |
| tx_pll_clk_out | Output | To be connected to tx_pll_clk input port, of cores without shared logic |
| rx_pll_rst_out | Output | To be connected to rx_pll_clk input port, of cores without shared logic |
| tx_rdclk_out | Output | 156.25Mhz reference clock for cores without shared logic. |
| rx_btval<n>[8:0] | Output | To be connected to rx_btval input port, of cores without shared logic |