1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

Using the core with a device-specific transceiver provides the functionality to implement the 1000BASE-X or 2500BASE-X PCS and PMA sublayers. Alternatively, it can be used to provide a GMII to SGMII bridge.

The core interfaces to a device-specific transceiver, which provides some of the PCS layer functionality such as 8B/10B encoding/decoding, the PMA Serializer/Deserializer (SerDes), and clock recovery. The following figure shows the PCS sublayer functionality and the major functional blocks of the core. A description of the functional blocks and signals is provided in subsequent sections.

Figure 1. Core Block Diagram Using a Device-Specific Transceiver Page-1 Sheet.1 Sheet.2 PCS Receive Engine and Syncronization PCS Receive Engineand Syncronization Sheet.3 PCS Transmit Engine PCS Transmit Engine Sheet.4 GMII Block GMII Block Sheet.5 Optional PCS Management Optional PCSManagement Sheet.6 Optional Auto-Negotiation OptionalAuto-Negotiation Sheet.7 To PMD Sublayer To PMDSublayer Sheet.8 X12779 X12779 Sheet.9 GMII to MAC GMIIto MAC Sheet.10 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.11 Tranceiver Transceiver Sheet.12 MDIO Interface MDIOInterface Standard Arrow.14 Standard Arrow.47 Standard Arrow.11 Standard Arrow.5 Standard Arrow.12 Standard Arrow.16 Standard Arrow.18 Standard Arrow.19 Standard Arrow.22 Standard Arrow.23 Standard Arrow.25