GMII Transmitter Logic (Zynq 7000 and 7 Series) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
When implementing an external GMII, the GMII transmitter signals are synchronous to their own clock domain. The core must be used with a TX elastic buffer to transfer these GMII transmitter signals onto the core 125 MHz (312.5 MHz in 2.5G mode) reference clock (gtx_clk when using the TBI; userclk2 when using the device-specific transceiver). A TX elastic buffer is provided for the 1000BASE-X or 2500BASE-X standard in the example design.

Use a combination of IODELAY elements on the data, and use BUFIO and BUFR regional clock routing for the gmii_tx_clk input clock

In this implementation, a BUFIO is used to provide the lowest form of clock routing delay from input clock to input GMII TX signal sampling at the device IOBs. Note, however, that this creates placement constraints; a BUFIO capable clock input pin must be selected, and all other input GMII TX signals must be placed in the respective BUFIO region. See the device data sheets for more information.

The clock is then placed onto regional clock routing using the BUFR component and the input GMII TX data immediately resampled. The IODELAY elements can be adjusted to fine-tune the setup and hold times at the GMII IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the XDC; these can be edited if required.