SGMII Adaptation Module Top Level - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The SGMII adaptation module is described in several hierarchical submodules as shown in the following figure. These submodules are each described in separate HDL files and are described in the following sections.

Figure 1. SGMII Adaptation Module SGMII Adaptation Module Tx Rate Adapt Clock Generation To GMII Tx input of core From GMII Rx output of core From Client MAC GMII/ Client PHY SGMII To Client MAC GMII/ Client PHY GMII sgmii_clk_en userclk2 (125 MHz reference clock) sgmii_clk_en sgmii_clk_r clk125m speed_is_10_100 speed_is_100 sgmii_clk_f clk125m sgmii_clk_en gmii_txd_in[7:0] gmii_txd_out[7:0] gmii_tx_en_in gmii_tx_en_out gmii_tx_er_in gmii_tx_er_out Rx Rate Adapt clk125m sgmii_clk_en gmii_rxd_out[7:0] gmii_rxd_in[7:0] gmii_rx_dv_out gmii_rx_dv_in gmii_rx_er_out gmii_rx_er_in Speed Control X12855