Receive Path Latency - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

As measured from a data octet input into the core on rxdata[7:0] from the serial transceiver interface (until that data appears on gmii_rxd[7:0] of the receiver side GMII), the latency through the core in the receive direction is six clock periods of userclk2.