Asynchronous LVDS Transceiver for UltraScale and Ultrascale+ - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

The LVDS transceiver block fully replaces the functionality otherwise provided by the device transceiver. This is only possible at a serial line rate of 1.25 Gbps. The following figure shows a block diagram of the asynchronous LVDS transceiver for UltraScale and UltraScale+ devices. This is split up into several sub-blocks which are described in further detail in the following sections.

Figure 1. Asynchronous LVDS Transceiver Block Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 8B/10B Decoder 8B/10BDecoder Sheet.3 8B/10B Encoder 8B/10BEncoder Sheet.4 RX Elastic Buffer RX Elastic Buffer Sheet.5 Serdes_1_to_10 Serdes_1_to_10 Sheet.6 10 to 8 Gearbox (tx_ten_to_eight) 10 to 8 Gearbox(tx_ten_to_eight) Sheet.7 <component_name>_lvds_transceiver <component_name>_lvds_transceiver Sheet.8 RX I/O Logic RX I/O Logic Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 RX data RX data Sheet.15 RX data valid RX data valid Sheet.16 RX data valid RX data valid Sheet.17 RX data RX data Sheet.18 Sheet.19 RX data RX data Sheet.20 TX I/O Logic TX I/O Logic Sheet.21 Sheet.22 Sheet.23 TX data TX data Sheet.24 Sheet.25 Sheet.26 Sheet.27 tx_p[0...2] tx_p[0...2] Sheet.28 tx_n[0...2] tx_n[0...2] Sheet.29 Sheet.30 Sheet.31 rx_p[0….2] rx_p[0….2] Sheet.32 rx_n[0….2] rx_n[0….2] Sheet.33 Clocking Logic Clocking Logic Sheet.34 Reset Sequence Reset Sequence Sheet.35 Sheet.36 BaseX_Byte BaseX_Byte Sheet.37 X17632-081816 X17632-081816

On the transmitter path, data sourced by the core netlist is routed through the 8B/10B Encoder to translate the 8-bit code groups into 10-bit data. The 10-bit data is then passed through the 10B8B Gearbox and the parallel data is then clocked out serially at a line rate of 1.25 Gbps.

The receiver path has additional complexity. Serial data received at 1.25 Gbps is routed in parallel to two RX_BITSLICEs. By comparing 4-bit parallel data from these RX_BITSLICEs the correct sampling point is computed for the incoming data stream and delays for RX_BITSLICEs adjusted accordingly. Soft logic in the serdes_1_to_10 module provides logic to find the correct sampling point of the received data by scanning the serial stream from the two parallel RX_BITSLICEs.

The Serdes_1_to_10 module provides 10-bit comma-aligned parallel data and a data valid signal at a higher clock rate of 312.5 MHz. The next block on the receiver path detects specific 8B/10B bit patterns (commas) and uses these to realign the 10-bit parallel data to contain unique 8B/10B code groups. These code groups are then routed through the 8B/10B decoder module to obtain the unencoded 8-bit code groups.

These 8-bit code groups are synchronous to 312.5 MHz local clock and are qualified with data valid. To convert this to the 125 MHz local clock, the clock correction buffer needs to be present which can insert or remove idles into or from the incoming data stream to compensate for ppm difference between the far end clock and local clock. This ppm compensation is handled by the RX elastic buffer.

The following files describe the top level of the hierarchal levels of the LVDS transceiver:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ synth/lvds_transceiver/<component_name>_lvds_transceiver.v