DRP and 1588 Support Ports - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following tables describe the signals for supporting 1588. These interfaces are available only when this core is used in conjunction with the Tri-Mode Ethernet MAC core (TEMAC).

See the 7 Series FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG168) for more details on the DRP signals.

Table 1. DRP Interface to Transceiver Ports
Signal Direction Description
drp_dclk In DRP interface clock, tied to gtrefclk_bufg for 7 series/Zynq devices and independent_clock_bufg for UltraScale+/UltraScale devices.
drp_req 1 Out DRP request
drp_gnt 1 In DRP grant
drp_den 1 Out DRP enable signal
drp_dwe 1 Out DRP write enable
drp_drdy 1 In Indicates DRP operation is complete
drp_daddr[8:0] 1 Out DRP address
drp_di[15:0] 1 Out DRP data from transceiver
drp_do[15:0] 1 In DRP data to transceiver
  1. Signals are synchronous to gtrefclk for 7 series devices and independent_clock for UltraScale+/UltraScale devices.
Table 2. 1588 Ports
Signal Direction Description
systemtimer_s_field[47:0] In 1588 System timer seconds value
systemtimer_ns_field[31:0] In 1588 System timer nanoseconds value
rxphy_s_field[47:0] Out 1588 timer PHY correction seconds value
rxphy_ns_field[31:0] Out 1588 timer PHY correction nanoseconds value
correction_timer[63:0] In Correction timer
rxphy_correction_timer[63:0] Out Modified correction timer