UltraScale Device LVDS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

This section provides general guidelines for creating synchronous SGMII designs using the UltraScale device LVDS. This enables direct connection to external PHY devices without the use of an FPGA transceiver.

To benefit from a detailed understanding of UltraScale clocking resources and SelectIO Resources, see UltraScale Architecture SelectIO Resources User Guide (UG571) and UltraScale Architecture Clocking Resources User Guide (UG572).