Transmit Path Latency - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

As measured from a data octet input into gmii_txd[7:0] of the transmitter side GMII (until that data appears on txdata[7:0] on the serial transceiver interface), the latency through the core in the transmit direction is 4 clock periods of userclk2.