Synchronous SGMII over LVDS Example Design (Applicable for Non-Versal Devices) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

Figure 1 shows the HDL example design that is provided for the SGMII overZynq 7000 and 7 series device LVDS implementation. The top level of the example design creates a specific example that can be simulated, synthesized and implemented. The 2.5G mode is not supported in this case. The core netlist in this implementation is identical to that of 1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver.