rx_eight_to_ten - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

RX 8b/10b gearbox converts 8-bit data to 10-bit data and then performs comma alignment resulting in aligned data being output from this module. The data is synchronous to a 312.5Mhz clock and is qualified with data valid at all stages.

The above block, combined with the CDR logic that is built into Advanced IO wizard, replaces the function of serdes_1_to_10 block present in UltraScale/UltraScale+ designs.

The following file describes the RX gearbox functionality: