8B/10B Decoder - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The implemented 8B/10B coding scheme is an industry-standard, DC-balanced, byte-oriented transmission code ideally suited for high-speed local area networks and serial data links. As such, the coding scheme is used in several networking standards, including Ethernet. The 8B/10B Decoder block is taken from AMD Application Note, Parameterizable 8B/10B Encoder (XAPP1122) provides two possible approaches: a choice of a block RAM-based implementation or a LUT-based implementation.

The SGMII LVDS example design uses the LUT-based implementation, but XAPP1112 can be used to swap this for the block RAM-based approach if this better suits device logic resources.

The following files describe the 8B/10B Decoder:

<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ synth/lvds_transceiver/