The example design delivered with the core is shown in SGMII/Dynamic Switching Using a Transceiver Example Design. The block level is designed so to be instantiated directly into customer designs and connects the physical-side interface of the core to an AMD UltraScale+™ /AMD UltraScale™ , Virtex 7, Kintex 7 or Artix 7 or Zynq 7000 device transceiver through the FPGA logic receive elastic buffer.
Note: The optional transceiver Control and Status ports
are not shown here. These ports have been brought up to the <component_name> module
level.