Integration of Zynq 7000 Device PS ENET0/1 Using Sync SGMII over LVDS - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows the connections and clock management logic required to interface the core (in Sync SGMII over LVDS) to the TEMAC core. The block level of the Example Design should be taken from the example design and instantiated for connection to the TEMAC core. Connections from a unique TEMAC core to SGMII port are identical and are shown in the following figure. The 2.5G mode is not supported in this case.

The following conditions apply to each connected TEMAC core and SGMII port pair:
  • The SGMII Adaptation module, as provided in the example design for the 1G/2.5G Ethernet PCS/PMA or SGMII core when generated to the SGMII standard, can be used to interface the two cores.
  • If both cores have been generated with the optional management interface, the MDIO port can be connected up to that of the TEMAC core, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
  • clk125 is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of the TEMAC core now operate in the same clock domain. This is the clock derived by MMCM and IBUFDS from differential reference clock.

The following figure shows a TEMAC core generated with the optional clock enable circuitry. This is recommended as the best way to connect the two cores together for efficient use of clock resources. See the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051).

Figure 1. Core Using SGMII over LVDS Connected to the TEMAC Core