Integration of the Zynq 7000 Device PS ENET0/1 Using Device Specific - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
The following figure shows the connections and clock management logic required to interface the core (in SGMII Configuration and MAC mode with the 7 series FPGA transceiver) to the Zynq 7000 device PS ENET0/1. The 2.5G mode is not supported in this case.

Features of this configuration include:

  • The SGMII Adaptation module, as provided in the example design for the core when generated to the SGMII standard and MAC mode, can be used to interface the two cores.
  • The MDIO port can be connected up to that of the Zynq 7000 device ENET0/1, allowing the MAC to access the embedded configuration and status registers of the 1G/2.5G Ethernet PCS/PMA or SGMII core.
  • Because of the receive elastic buffer, the entire GMII (transmitter and receiver paths) is synchronous to a single clock domain. Therefore, userclk2 is used as the 125 MHz reference clock for both cores, and the transmitter and receiver logic of the Zynq 7000 device PS ENET0/1 now operate in the same clock domain.
Figure 1. Zynq 7000 Device ENET0/1 Extended to Include SGMII Using GTX Transceiver