Device Specific Transceiver Receive Elastic Buffers - 16.2 English - PG047

The following figure shows the transceiver receive elastic buffer depths and thresholds in AMD UltraScale+™ , AMD UltraScale™ architecture, AMD Zynq™ 7000, and 7 series families. Each FIFO word corresponds to a single character of data (equivalent to a single byte of data following 8B/10B decoding).

Consider the example, where the shaded area represents the usable buffer availability for the duration of frame reception.

• If the buffer is filling during frame reception, there are 61 - 36 = 25 FIFO locations available before the buffer reaches the overflow mark.
• If the buffer is emptying during reception, then there are 33-8 = 25 FIFO locations available before the buffer reaches the underflow mark.

This analysis assumes that the buffer is approximately at the half-full level at the start of the frame reception. As shown, there are two locations of uncertainty, above and below the exact half-full mark of 32, resulting from the clock correction decision, and is based across an asynchronous boundary.

Because there is a worst-case scenario of one clock edge difference every 5000 clock periods, the maximum number of clock cycles (bytes) that can exist in a single frame passing through the buffer before an error occurs is:

5000 x 25=125000 bytes