The following figure shows the most common reset structure for the core with TBI. The grayed
out region indicates the logic that is activated under certain conditions based on the
core configuration.
Figure 1. Reset Structure for Core with TBI
Ethernet 1000BASE-X PCS/PMA or SGMII
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Sheet.14
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Sheet.22
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Sheet.30
Sheet.37
gpcs_pma_gen
gpcs_pma_gen
Sheet.47
RESET
RESET
Sheet.48
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x13216
x13216
Standard Arrow.223
Standard Arrow.65
Standard Arrow.78
Standard Arrow.127
Standard Arrow.55
Standard Arrow.8
Standard Arrow.14
Sheet.90
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Reset Sync
ResetSync
Sheet.95
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Sheet.98
Reset Sync
ResetSync
Sheet.103
soft_reset
soft_reset
Sheet.106
component_name_block
component_name_block
Sheet.110
Sheet.111
Sheet.112
Sheet.113
Reset Sync
ResetSync
Sheet.115
Synchronization Logic
Synchronization Logic
Sheet.116
IDELAY LOGIC
IDELAYLOGIC
Sheet.1
SGMII Adapt
SGMIIAdapt
Sheet.8
Sheet.9
Sheet.12
Sheet.13
Reset Sync
ResetSync
Sheet.82
Sheet.42
Sheet.43
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Sheet.45
Sheet.46
OR
OR
Sheet.102
Management Logic
Management Logic
Sheet.108
An Logic
An Logic
Sheet.109
Tx Logic
Tx Logic
Sheet.114
Rx Logic
Rx Logic
Sheet.27
TBI Logic
TBI Logic
Sheet.99
Sheet.100