Core with Transceiver - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
The loopback path is implemented in the core as shown in the following figure. When placed into loopback, the data is routed from the transmitter path to the receiver path at the last possible point in the core. This point is immediately before the device-specific transceiver (or LVDS transceiver) interface. When placed in loopback, the core creates a constant stream of Idle code groups that are transmitted through the serial or GTP transceiver in accordance with the IEEE 802.3-2008 specification.

Earlier versions (before v5.0) of the core implemented loopback differently. The serial loopback feature of the device-specific transceiver was used by driving the loopback[1:0] port of the device-specific (serial or GTP) transceiver. This is no longer the case, and the loopback[1:0] output port of the core is now permanently set to logic “00.” However, for debugging purposes, the loopback[1:0] input port of the device-specific transceiver can be directly driven by the user logic to place it in either parallel or serial loopback mode.

Note: Loopback is not supported by the core when RxGmiiClkSrc=RXOUTCLK.
Figure 1. Loopback Implementation when Using the Core with Device-Specific Transceivers Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 PCS TX Engine PCS TX Engine Sheet.3 Device Specific Transceiver DeviceSpecificTransceiver Sheet.4 1G/2.5G Ethernet PCS/PMA or SGMII Core 1G/2.5G Ethernet PCS/PMA or SGMII Core Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 TX TX Sheet.12 RX RX Sheet.15 Loopback occurs in core Loopback occurs in core Sheet.16 PCS RX Engine PCS RX Engine Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Idle Stream Idle Stream Sheet.22 loopback control loopback control Sheet.23 X12798-031417 X12798-031417 Standard Arrow.19 Standard Arrow.6 Connector Dot Sheet.29 Standard Arrow.47 Connector Dot.14 Sheet.36 Sheet.26 Sheet.27 Sheet.31 Sheet.33 Sheet.37